It is important for the characteristics of a switch that is used via an analog signal not to distort the analog signal through the on-resistance of the switch. An analog-to-digital converter (ADC) has a switch circuit and a sampling capacitor. In the ADC, in the case where a distortion occurs in a signal due to the switch circuit configured to sample an analog signal, the conversion characteristics of the ADC are worsened accordingly. A transistor that is used to sample an analog signal by a switch circuit of the ADC is referred to as a sampling transistor. Hereinafter, not limited to the ADC, a transistor that forms an analog switch turning on or off an analog signal is referred to as a sampling transistor here. In other words, what is referred to as a sampling transistor is not limited to the ADC, and whatever is used as a main switch of an analog switch circuit may be referred to as a sampling transistor.
As a switch circuit configured to sample an analog signal, a CMOS switch having an NMOS and a PMOS connected in parallel is used, but a gate-source voltage Vgs of the NMOS and PMOS changes in accordance with an input voltage. Because of this, in the CMOS switch, the on-resistance changes depending on the input voltage and a distortion occurs in an analog signal.
As a technique for improving accuracy of analog signal processing by reducing the distortion of a signal, which occurs due to a change in the on-resistance depending on the input voltage, a bootstrap switch (hereinafter, referred to as BSW) is known. It is possible for the BSW to maintain the gate-source voltage of a sampling transistor almost constant. By using the BSW in a switch circuit of an analog signal, it is possible to improve the accuracy of analog signal processing by reducing the distortion of a signal, which occurs due to a change in the on-resistance.
In recent years, the operation voltage is lowered remarkably in order to reduce power consumption and further, miniaturization of a circuit element is in progress, and therefore, the withstand voltage of a circuit element is lowered. The withstand voltage of the transistor forming the BSW is also lowered and the withstand voltage of the transistor of the BSW has lowered below a value twice the power source voltage. In the above-described BSW, if the input signal swings fully between 0 V and a power source voltage VDD, a case may occur where a voltage about twice the power source voltage is applied to a transistor, which is a part of the circuit, when the sampling transistor makes a transition from on to off.
In order to avoid this problem of withstand voltage, the control circuit configured to reduce the gate voltage of the sampling transistor to a low potential when the sampling transistor is turned off is formed by transistors in two stages connected in series, and the voltage that is applied to each transistor is reduced.